KW45

恩智浦
RMB

Overview

KW45’s three-core architecture integrates a 96 MHz CM33 application core, dedicated CM3 radio core and an isolated EdgeLock Secure Enclave. The Flash-based radio core with dedicated SRAM delivers a highly configurable and upgradeable software-implemented radio, freeing resources on the main core for customer application space.

The Bluetooth Low Energy 5.3-compliant radio supports up to 24 simultaneous secure connections. The EdgeLock Secure Enclave’s isolated execution environment provides a set of cryptographic accelerators, key store operations and secure lifecycle management that minimizes main core security responsibilities.

The KW45 MCU additionally integrates FlexCAN, helping enable seamless integration into an automobile’s in-vehicle or industrial CAN communication network. The FlexCAN module can support CAN’s flexible data rate (CAN FD) for increased bandwidth and lower latency.

Features

Application Core
Up to 96 MHz Arm Cortex-M33 core
1 MB Program Flash
128 kB SRAM
Nested Vectored Interrupt Controller (NVIC)

Radio Core
Dedicated CM3 core
Secure 256 kB Flash for authenticated NXP Bluetooth Low Energy controller stack firmware
88 kB dedicated SRAM
2.4 GHz Bluetooth Low Energy Version 5.3 upgradeable radio supporting up to 24 simultaneous hardware connections in any central/peripheral combination
–106 dBm 125 kbps Long Range Receive Sensitivity
–102 dBm 500 kbps Long Range Receive Sensitivity
–97.5 dBm 1 Mbps Receive Sensitivity
–95 dBm 2 Mbps Receiver Sensitivity
Programmable Transmit Output Power up to +10 dBm
Data Rates: 125 kbps, 500 kbps, 1 Mbps and 2 Mbps
Modulation Types: 2 Level FSK, GFSK, MSK, GMSK
On-chip balun with single ended bidirectional RF port

Features

802.15.4 (Zigbee, Thread)

Application Note

• Automotive

— Secure Car Access

— Keyless Entry

— Passive Entry/Passive Start (PEPS) Systems

— Wireless Battery Management Systems (WBMS)

• Industrial/IoT

— Positioning/Localization

— Building Control and Monitoring

— Process/Factory Automation

Core Type

Arm® Cortex®-M33

CPU Clock Speed

__

CPU Architecture

__

CPU Features

__

Bluetooth Version

5.3

Operating Frequency [Max] (MHz)

96 MHz

Flash (kB)

256

Cache

-

SRAM (kB)

__

EEPROM (kB)

__

Debugging

__

Upgrade Type

Manual

Crystal

no

on chip (PLL)

no

crystal (optional)

no

on-chip RC

no

External clock

no

Timers [Number, bits]

32 MHz supported for Bluetooth LE and Generic FSK modes

Real-Time Clock

32.768 kHz Crystal Oscillator

Watchdog timer

no

GPIO

__

Pins

__

Pitch

__

Channels

__

ADC [Number, bits]

__

True Random Number Generator

__

Analog comp

no

low-power comp

no

Temperature sensor

no

NFC Tag

__

SPI

Two LSPI

DAC [Number, bits]

__

UART

Two LPUART

SSI

__

PWM [Number, bits]

__

I2C

Two Low Power I2C (LPI2C) modules supporting the System Management Bus (SMBus) Specification, version 2

TWI

no

QDEC

-

PDM

-

USB

no

SPI

Two Low Power SPI modules and one MIPI-I3C module

Quad SPI

-

I2S

no

Debug interface

-

Human Machine Interface

-

Programmable channels

__

Fixed channels

__

Channel groups

__

Supply Voltage [Min to Max] (V)

__

no

On-chip VBUS

no

Regulated supply for external components

-

Power fail

no

Crypto Accelerator

__

Public Key Hardware Accelerator

__

Accelerator

__

Security

__

__

Current

__

Sensor Controller

__

Standby

__

Transceiver Compatible

__

Receiver Sensitivity

–95 dBm 2 Mbps Receiver Sensitivity

Output Power

+10 dBm

Frequency Regulation

__

Protocols

-

Bluetooth 5 PHYs

-

bluetooth 5.1 support

-

Dimension

6 x 6 mm 40HVQFN,7 x 7 mm 48HVQFN

Package Type

HVQFN, 48HVQFN

DSP RAM

__

DSP Clock Speed

__

DSP Clock Speed

__

Voice Services

__

General

__